The present invention relates to a semiconductor device. More specifically, the present invention relates to an electrostatic discharge protected transistor.
In recent years, a silicide structure has been widely adopted for a semiconductor device so as to prevent an increase in parasitic resistance due to a reduction in a thickness of a diffused layer following a scale down of a metal oxide semiconductor (MOS) device. Since the silicide structure has the property of reducing diffusion resistance, the parasitic resistance can be reduced. However, if a silicide film is formed on a plurality of element formation regions, a current tends to flow between the adjacent element formation regions. Due to this, if the silicide structure is applied to elements, such as electrostatic discharge protected transistors, each of which needs to suddenly carry a high current, in particular, the current disadvantageously concentrates on one point and thermal destruction eventually occurs. Therefore, there is proposed a method for preventing current concentration by sub-dividing the electrostatic discharge protected transistors into sets (semiconductor moats), and keeping a high resistance between the adjacent electrostatic discharge protected transistors (see, for example, U.S. Pat. No. 4,825,280).
A conventional electrostatic discharge protected transistor sub-divided into sets according to the semiconductor moats will now be described with reference to FIGS. 10 and 11A, 11B, and 11C.
FIG. 10 is a plan view which depicts the conventional electrostatic discharge protected transistor which includes a silicide film. FIGS. 11A to 11C are sections that depict the conventional electrostatic discharge protected transistor. Specifically, FIG. 11A is a section taken along a line A4—A4 of FIG. 10, FIG. 11B is a section taken along a line B4—B4 of FIG. 10, and FIG. 11C is a section taken along a line C4—C4 of FIG. 10.
As shown in FIG. 10, the conventional electrostatic discharge protected transistor is constituted so that a plurality of transistors 121, 122 and 123 are arranged to share a common gate electrode among them.
As shown in FIG. 11A, each of the transistors 121 to 123 includes element isolation regions 102 of a shallow trench isolation (STI) structure each of which has an insulating film buried in a trench provided in a p-type semiconductor substrate 101 that consists of silicon, a gate insulating film 103 which is provided on an active region of the p-type semiconductor substrate 101 and which is composed of a silicon oxide film, a gate electrode 104 which is provided on the gate insulating film 103 and which is composed of a doped polysilicon film, and an on-gate silicide film 105G which is formed on the gate electrode 104.
Each of the transistors 121 to 123 also includes n-type low-concentration diffused layers 106 which are formed in regions of the active region of the semiconductor substrate 101 which regions are located below sides of the gate electrode 104, respectively, insulating sidewall spacers 107 which are formed on side surfaces of the gate electrode 104, respectively, an n-type high-concentration drain region 108D (108D1, 108D2, or 108D3) and an n-type high-concentration source region 108S (108S1, 108S2, or 108S3) which are formed in regions of the active region of the semiconductor substrate 101 which regions are located below respective sides of the sidewalls 107, an on-drain silicide film 105D (105D1, 105D2, or 105D3) which is formed on the n-type high-concentration drain region 108D, and an on-source silicide film 105S (105S1, 105S2, or 105S3) which is formed on the n-type high-concentration source region 108S.
Further, each transistor includes an interlayer insulating film 109 formed on the semiconductor substrate 101, a drain contact 110D, (110D1, 110D2, or 110D3) which penetrates the interlayer insulating film 109 on the n-type high-concentration drain region 108D and which reaches the on-drain silicide film 105D, a source contact 110S (110S1, 110S2, or 110S3) which penetrates the interlayer insulating film 109 on the n-type high-concentration source region 108S and which reaches the on-source silicide film 105S, metal wirings 111D and 111S which are formed on the interlayer insulating film 109 so as to be connected to the drain contact 110D and the source contact 110S, respectively, and each of which consists of Al or Al alloy, and an interlayer insulating film 112 formed on the interlayer insulating film 109 and the metal wirings 111D and 111S.
With this structure, the on-drain silicide films 105D1, 105D2, and 105D3, the n-type high-concentration drain regions 108D1, 108D2, and 108D3, the on-source silicide films 105S1, 105S2, and 105S3, and the n-type high-concentration source regions 108S1, 108S2, and 108S3 are isolated from one another by the element isolation regions 102, respectively. The entire electrostatic discharge protected transistor can, therefore, prevent occurrence of local current concentration.
However, according to the conventional art, each of the transistors 121 to 123 is sub-divided into sub-transistors corresponding to the respective semiconductor moats. It is, therefore, necessary to provide regions for isolating diff-used layers of the respective sub-transistors from one another within each of the transistors 121 to 123. This disadvantageously increases a total area of the electrostatic discharge protected transistor.